This invention relates to programmable logic devices. More particularly, this invention relates to circuitry for powering down groups of memory cells in a programmable logic device and for resetting the states of the memory cells in a programmable logic device upon device initialization.
Programmable logic devices are integrated circuits that may be programmed by a user to perform various logic functions. Some programmable logic devices are based upon random access memory cells that may be loaded with programming data to configure the programmable logic components contained in such devices. Memory cells in a device of this type are often organized in the form of an array of rows and columns of cells.
In programmable logic devices based on programmable memory cells, it is sometimes necessary to deactivate a row of cells. For example, if a defective memory cell is found in a row during device testing, that row of cells may be removed from active use by powering down the cells in the row. However, conventional circuits for deactivating rows of memory cells are not always capable of completely shutting down the memory cells.
In addition, to properly initialize a programmable logic device, all of its memory cells must be placed in a known state. This is typically done by programming a zero into each memory cell. However, maintaining the ability to program each cell with a zero after power has been applied to the device imposes restrictions on the minimum power supply level (Vcc) that may be used. If Vcc is too low, it will be difficult to program the device properly. Although a large value of Vcc may be used, this increases power consumption.
It is therefore an object of the present invention to provide a programmable logic device memory array circuit that allows a group of memory cells to be powered down and that allows the memory cells on a device to be effectively reset by maintaining the cells at a logical zero during device initialization.